How to use the command "iverilog" (with examples)

iverilog path/to/source.v -o path/to/executable

Motivation: This command is useful when you want to compile a Verilog HDL source file (source.v) into an executable program that can be used for simulation. The -o flag is used to specify the output file name, and path/to/executable specifies the location where the compiled executable should be saved.

Explanation:

• iverilog: This is the command to execute the iverilog compiler.
• path/to/source.v: Specifies the path to the Verilog HDL source file that needs to be compiled.
• -o path/to/executable: Specifies the output file name and the location where the compiled executable should be saved.

Example Output:

Compiled successfully. Executable saved as 'path/to/executable'.

2: Compile a source file into an executable while displaying all warnings

iverilog path/to/source.v -Wall -o path/to/executable

Motivation: When compiling a Verilog HDL source file, it is important to be aware of any warnings that may indicate potential issues in the code. Using the -Wall flag, the iverilog compiler will display all warnings encountered during the compilation process.

Explanation:

• iverilog: This is the command to execute the iverilog compiler.
• path/to/source.v: Specifies the path to the Verilog HDL source file that needs to be compiled.
• -Wall: Enables the display of all warnings encountered during compilation.
• -o path/to/executable: Specifies the output file name and the location where the compiled executable should be saved.

Example Output:

Warning: unused signal 'data_out' (source.v:10)
Compiled successfully with warnings. Executable saved as 'path/to/executable'.

3: Compile and run explicitly using the VVP runtime

iverilog -o path/to/executable -tvvp path/to/source.v

Motivation: The iverilog compiler can directly compile the source file and execute it using the VVP (Verilog Value Change Dump) runtime. This allows for a quick and seamless simulation of the Verilog code.

Explanation:

• iverilog: This is the command to execute the iverilog compiler.
• -o path/to/executable: Specifies the output file name and the location where the compiled executable should be saved.
• -tvvp: Specifies the use of the VVP runtime for simulation.
• path/to/source.v: Specifies the path to the Verilog HDL source file that needs to be compiled and executed.

Example Output:

Simulation started...
Simulation finished successfully.

4: Compile using Verilog library files from a different path

iverilog path/to/source.v -o path/to/executable -Ipath/to/library_directory

Motivation: Verilog libraries contain commonly used modules and definitions. Sometimes, it’s necessary to include Verilog library files from a different location than the current directory. The -I flag in iverilog is used to specify the path to the directory containing the library files.

Explanation:

• iverilog: This is the command to execute the iverilog compiler.
• path/to/source.v: Specifies the path to the Verilog HDL source file that needs to be compiled.
• -o path/to/executable: Specifies the output file name and the location where the compiled executable should be saved.
• -Ipath/to/library_directory: Specifies the path to the directory containing the Verilog library files.

Example Output:

Compiled successfully using Verilog library files from 'path/to/library_directory'. Executable saved as 'path/to/executable'.

5: Preprocess Verilog code without compiling

iverilog -E path/to/source.v

Motivation: Sometimes, it is necessary to preprocess Verilog code without actually compiling it. This can be useful for verifying the correctness of preprocessing directives and generating preprocessed output files for further analysis.

Explanation:

• iverilog: This is the command to execute the iverilog compiler.
• -E: Specifies that the Verilog code should be preprocessed without compiling.
• path/to/source.v: Specifies the path to the Verilog HDL source file that needs to be preprocessed.

Example Output:

Preprocess completed successfully. Preprocessed Verilog code saved as 'source_preprocessed.v'.

Conclusion

In this article, we explored different use cases of the iverilog command for preprocessing and compiling Verilog HDL code. We discussed how to compile a source file into an executable, compile with warnings, compile and run using the VVP runtime, compile using Verilog library files from a different path, and preprocess Verilog code without compiling. Each use case was accompanied by a motivation, explanation of the arguments, and example output. By understanding and effectively using these different command options, Verilog developers can compile and simulate their code with ease.