Verilator Command Examples (with examples)

Build a specific C project in the current directory

verilator --binary --build-jobs 0 -Wall path/to/source.v

Motivation

This use case is helpful when we want to convert a Verilog or SystemVerilog design into a binary executable. By using the --binary flag, Verilator will produce a standalone C++ model that can be executed after compiling.

Explanation

• --binary: Specifies that Verilator should generate a binary executable.
• --build-jobs 0: This argument limits the number of parallel build jobs to zero, which means that Verilator will build the project using a sequential compilation process.
• -Wall: Enables all warning messages during the compilation process.
• path/to/source.v: Specifies the path to the Verilog/SystemVerilog source file that needs to be built.

Example Output

After running the command, Verilator will generate the binary executable for the specified Verilog or SystemVerilog design file.

Create a C++ executable in a specific folder

verilator --cc --exe --build --build-jobs 0 -Wall path/to/source.cpp path/to/output.v

Motivation

This use case is useful when we want to convert a Verilog or SystemVerilog design along with a C++ testbench into a C++ executable. By using the --cc and --exe flags, Verilator will generate the necessary files for compiling and executing the C++ model.

Explanation

• --cc: Specifies that Verilator should generate a C++ model.
• --exe: Indicates that Verilator should generate files for creating a C++ executable.
• --build: Request Verilator to perform the build process.
• --build-jobs 0: Restricts the number of parallel build jobs to zero, ensuring a sequential compilation process.
• -Wall: Enables all warning messages during the compilation process.
• path/to/source.cpp: Specifies the path to the C++ testbench file.
• path/to/output.v: Specifies the path to the Verilog/SystemVerilog design file.

Example Output

After running the command, Verilator will generate the necessary files to compile and execute the C++ model, including the C++ testbench and the Verilog/SystemVerilog design file.

Perform linting over a code in the current directory

verilator --lint-only -Wall

Motivation

Linting is a crucial step in the hardware design process as it helps identify potential issues or violations of coding standards. This use case allows us to perform linting on Verilog or SystemVerilog code to ensure its quality.

Explanation

• --lint-only: Specifies that Verilator should only perform linting and not generate any executable model.
• -Wall: Enables all warning messages during the linting process.

Example Output

After running the command, Verilator will generate linting messages for any issues or violations found in the Verilog/SystemVerilog code.

Create XML output about the design to feed into other tools

verilator --xml-output -Wall path/to/output.xml

Motivation

Generating XML output about the design facilitates compatibility with other tools that may require such information. This use case allows us to create XML output that contains details about the files, modules, instance hierarchy, logic, and data types of the Verilog/SystemVerilog design.

Explanation

• --xml-output: Instructs Verilator to generate XML output about the design.
• -Wall: Enables all warning messages during the process.
• path/to/output.xml: Specifies the path and name of the XML output file.

Example Output

After running the command, Verilator will generate an XML file containing detailed information about the Verilog/SystemVerilog design. This XML output can then be used as input for other tools in the hardware design workflow.